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1/40 september 2004 m41st87y M41ST87W 5.0, 3.3, or 3.0v, 1280 bit (160 x8) secure serial rtc and nvram supervisor with tamper detection features summary 5.0, 3.3, or 3.0v operating voltage serial interface supports i 2 c bus (400khz) nvram supervisor for external lpsram 2.5 to 5.5v oscillator operating voltage automatic switch-over and deselect circuitry choice of power-fail deselect voltages ? m41st87y: v cc = 4.75 to 5.5v; ths bit = '1': 4.50v v pfd 4.75v v cc = 4.5 to 5.5v; ths bit = '0': 4.20v v pfd 4.50v ? M41ST87W: v cc = 3.0 to 3.6v; ths bit = '1': 2.8v v pfd 3.0v v cc = 2.7 to 3.6v; ths bit = '0': 2.55v v pfd 2.70v two independent power-fail comparators (1.25v reference) counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 128 bytes of general purpose ram programmable alarm and interrupt function (valid even during battery back-up mode) programmable watchdog timer unique electronic serial number (8-byte) 32khz frequency output available upon power-on microprocessor power-on reset battery low flag ultra-low battery supply current of 500na (typ) security features tamper indication circuits with timestamp and ram clear lpsram clear function (tp clr ) packaging includes a 28-lead, embedded crystal soic oscillator stop detection figure 1. package 28-pin, (300mil) sox28 (mx) embedded crystal
m41st87y, M41ST87W 2/40 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. 28-pin, 300mil soic (mx) connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-wire bus characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 stop data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10.read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11.alternate read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12.write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13.write cycle timing: rtc & external sram control signals . . . . . . . . . . . . . . . . . . . . 13 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 tamper detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 tamper register bits (tamper 1 and tamper 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 tamper enable bits (teb1 and teb2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 tamper bits (tb1 and tb2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 tamper interrupt enable bits (tie1 and tie2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 tamper connect mode bit (tcm1 and tcm2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 tamper polarity mode bits (tpm1 and tpm2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 14.tamper detect connection options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. tamper detection truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 15.tamper detect output options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 16.basic tamper detect options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 tamper detect sampling (tds1 and tds2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3/40 m41st87y, M41ST87W tamper current hi/tamper current lo (tchi/tclo1 and tchi/tclo2) . . . . . . . . . . . . . . . . . . . 17 ram clear (clr1 and clr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ram clear external (clr1 ext and clr2 ext ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. tamper detection current (normally closed - tcm x = '0') . . . . . . . . . . . . . . . . . . . . . . . 17 figure 17.tamper detect sampling options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 18.tamper current options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 19.tamper output timing (with clr1 ext or clr2 ext = '1') . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. tamper detect timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 20.ram clear hardware hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 tamper detection operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 internal tamper pull-up/down current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 tamper event time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 timekeeper? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. timekeeper? register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 calibrating the clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 21.crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 22.calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 23.alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 24.back-up mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 full-time 32khz square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 reset inputs (rstin1 & rstin2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 25.rstin1 & rstin2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. reset ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 power-fail comparators (1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 power-fail outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 output driver pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 battery low warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 t rec bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 electronic serial number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 initial power-on defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10. century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 11. t rec definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 12. default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
m41st87y, M41ST87W 4/40 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. dc and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 26.ac testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 27.power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 28.sox28 ? 28-lead plastic small outline, 300mils, embedded crystal outline. . . . . . . . . 37 table 18. sox28 ? 28-lead plastic small outline, 300mils, embedded crystal, mechanical data 37 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 20. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5/40 m41st87y, M41ST87W summary description the m41st87y/w serial timekeeper ? /con- troller sram is a low power 1280-bit, static cmos sram organized as 160 bytes by 8 bits. a built-in 32.768 khz oscillator (internal crystal-controlled) and 8 bytes of the sram (see table 6., page 23 ) are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 11 bytes of ram provide calibration, status/control of alarm, watchdog, tamper, and square wave functions. 8 bytes of rom and final- ly 128 bytes of user ram are also provided. ad- dresses and data are transferred serially via a two line, bi-directional i 2 c interface. the built-in ad- dress register is incremented automatically after each write or read data byte. the m41st87y/ w has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. the energy needed to sustain the sram and clock op- erations can be supplied by a small lithium button- cell supply when a power failure occurs. functions available to the user include a non-vol- atile, time-of-day clock/calendar, alarm interrupts, tamper detection, watchdog timer, and pro- grammable square wave output. other features include a power-on reset as well as two addition- al debounced inputs (rstin1 and rstin2 ) which can also generate an output reset (rst ). the eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour bcd for- mat. corrections for 28, 29 (leap year), 30 and 31 day months are made automatically. security features two fully independent tamper detection inputs al- low monitoring of multiple locations within the sys- tem. programmable bits provide both, ?normally open? and ?normally closed? switch monitoring. time stamping of the tamper event is automatical- ly provided. there is also an option allowing data stored in either internal memory (128 bytes), and/ or external memory to be cleared, protecting sen- sitive information in the event tampering occurs. by embedding the 32khz crystal in the package, the clock is completely isolated from external tam- pering. an oscillator fail bit (of) is also provided to ensure correct operation of the oscillator. the m41st87y/w is supplied in a 28-pin, 300mil soic package (mx) which includes an embedded 32khz crystal. the soic package is shipped in plastic anti-static tubes or in tape & reel form. the 300mil, embedded crystal soic requires only a user-supplied battery to provide non-volatile op- eration.
m41st87y, M41ST87W 6/40 figure 2. logic diagram note: 1. open drain output 2. programmable output (open drain or full-cmos) figure 3. 28-pin, 300mil soic (mx) connections note: no function (nf) pins should be tied to v ss . pins 1, 2, 3, and 4 are internally shorted together. table 1. signal names note: 1. open drain output 2. programmable output (open drain or full-cmos) 3. should be connected to v ss . ai07023 scl v cc m41st87y M41ST87W ex v ss v bat sda rstin1 irq/out (1) sqw/ft (2) wdi rstin2 tp1 in pfi 2 tp2 in pfi 1 e con rst (1) pfo 1 (2) pfo 2 (2) v out f 32k (1) tp clr ai07025b 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 rstin1 rstin2 pfi 2 nf nc sqw/ft wdi nf nc irq/out f 32k v out tp1 in ex pfi 1 scl tp clr pfo 1 e con v ss v bat tp2 in sda rst nf nf v cc m41st87y M41ST87W pfo 2 e con conditioned chip enable output ex external chip enable irq /out (1) interrupt/out output (open drain) pfi 1 power fail input 1 pfi 2 power fail input 2 pfo 1 (2) power fail output 1 pfo 2 (2) power fail output 2 rst (1) reset output (open drain) rstin1 reset 1 input rstin2 reset 2 input scl serial clock input sda serial data input/output sqw/ft (2) square wave output/frequency te s t wdi watchdog input v cc supply voltage v out voltage output v ss ground f 32k (1) 32khz square wave output (open drain) tp1 in tamper pin 1 input tp2 in tamper pin 2 input tp clr tamper pin ram clear v bat positive battery pin input nf (3) no function nc no connect
7/40 m41st87y, M41ST87W figure 4. block diagram note: 1. open drain output. 2. programmable output (open drain or full-cmos); if open drain option is selected and if pulled-up to supply other than v cc , this supply must be equal to, or less than 3.0v when v cc = 0v (during battery back-up mode). ai07026 compare v pfd v cc v out compare v so v out v bl bl compare crystal i 2 c interface real time clock calendar 128 bytes user ram 8 bytes rom rtc w/alarm & calibration watchdog square wave tamper sda scl 1.25v pfi 1 pfi 2 pfo 1 (2) pfo 2 (2) rstin1 por sqw/ft (2) rst (1) wdi tpx in wds tie x clr x clrx ext afe ofie irq/out (1) v bat 32khz oscillator tp clr f 32k (1) compare compare rstin2 ex e con (internal) 1.25v (internal)
m41st87y, M41ST87W 8/40 figure 5. hardware hookup ai07027 v cc pfo 1 ex scl m41st87y/w wdi rstin1 rstin2 pfi 1 pfi 2 v ss v bat f 32k irq/out sqw/ft rst v out e con sda unregulated voltage inhibit 5v regulator v cc v in inhibit 3.3v regulator v cc v in tp1 in tp clr tp2 in pushbutton reset for monitoring of additional voltage sources pfo 2 low-power sram v cc e to rst to led display to nmi to int to 32khz r1 r2 r3 r4
9/40 m41st87y, M41ST87W operating modes the m41st87y/w clock operates as a slave de- vice on the serial bus. access is obtained by im- plementing a start condition followed by the correct slave address (d0h). the 160 bytes con- tained in the device can then be accessed sequen- tially in the following order: 00h. tenths/hundredths of a second regis- ter 01h. seconds register 02h. minutes register 03h. century/hours register 04h. day register 05h. date register 06h. month register 07h. year register 08h. control register 09h. watchdog register 0ah-0eh. alarm registers 0fh. flag register 10h-12h. reserved 13h. square wave 14h. tamper register 1 15h. tamper register 2 16h-1dh. serial number (8 bytes) 1eh-1fh. reserved (2 bytes) 20h-9fh. user ram (128 bytes) the m41st87y/w clock continually monitors v cc for an out-of-tolerance condition. should v cc fall below v pfd , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. when v cc falls below v so , the device automati- cally switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). for more information on battery storage life refer to application note an1012. 2-wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a bi-direction- al data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. ? changes in the data line, while the clock line is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition.
m41st87y, M41ST87W 10/40 data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? the device that controls the message is called ?master.? the de- vices that are controlled by the master are called ?slaves.? acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat- ed clock pulse. a slave receiver which is ad- dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low dur- ing the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition. figure 6. serial bus data transfer sequence figure 7. acknowledgement sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
11/40 m41st87y, M41ST87W figure 8. bus timing requirements sequence table 2. ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of scl. symbol parameter (1) min max unit f scl scl clock frequency 0 400 khz t buf time the bus must be free before a new transmission can start 1.3 s t expd ex to e con propagation delay m41st87y 10 ns M41ST87W 15 ns t f sda and scl fall time 300 ns t hd:dat (2) data hold time 0 s t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t high clock high period 600 ns t low clock low period 1.3 s t r sda and scl rise time 300 ns t su:dat data setup time 100 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:sto stop condition setup time 600 ns ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
m41st87y, M41ST87W 12/40 read mode in this mode the master reads the m41st87y/w slave after setting the slave address (see figure 9., page 12 ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. next the start condition and slave ad- dress are repeated followed by the read mode control bit (r/w =1). at this point the master trans- mitter becomes the master receiver. the data byte which was addressed will be trans- mitted and the master receiver will send an ac- knowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the m41st87y/w slave transmitter will now place the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the ad- dress pointer is incremented to an+2. this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter (see figure 10., page 12 ). the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei- ther due to a stop condition or when the pointer increments to a non-clock or ram address. note: this is true both in read mode and write mode. an alternate read mode may also be implement- ed whereby the master reads the m41st87y/w slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 11., page 13 ). figure 9. slave address location figure 10. read mode sequence ai00602 r/w slave address start a 01000 11 msb lsb ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack
13/40 m41st87y, M41ST87W figure 11. alternate read mode sequence write mode in this mode the master transmitter transmits to the m41st87y/w slave receiver. bus protocol is shown in figure 12., page 13 . following the start condition and slave address, a logic '0' (r/ w =0) is placed on the bus and indicates to the ad- dressed device that word address an will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the m41st87y/w slave receiver will send an acknowledge clock to the master transmitter af- ter it has received the slave address (see figure 9., page 12 ) and again after it has received the word address and each data byte. figure 12. write mode sequence figure 13. write cycle timing: rtc & external sram control signals ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address ai03663 ex e con texpd texpd
m41st87y, M41ST87W 14/40 data retention mode with valid v cc applied, the m41st87y/w can be accessed as described above with read or write cycles. should the supply voltage decay, the m41st87y/w will automatically deselect, write protecting itself (and any external sram) when v cc falls between v pfd (max) and v pfd (min) (see figure 27., page 36 , table 17., page 36 ). this is accomplished by internally inhibiting access to the clock registers. at this time, the reset pin (rst ) is driven active and will remain active until v cc returns to nominal levels. external ram access is inhibited in a similar man- ner by forcing e con to a high level. this level is within 0.2 volts of the v bat . e con will remain at this level as long as v cc remains at an out-of-tol- erance condition. when v cc falls below the bat- tery back-up switchover voltage (v so ), power input is switched from the v cc pin to the battery, and the clock registers and external sram are maintained from the attached battery supply. all outputs become high impedance. the v out pin is capable of supplying 100a (for M41ST87W) or 150a (for m41st87y) of current to the attached memory with less than 0.3 volts drop under this condition. on power up, when v cc returns to a nominal value, write protection continues for t rec by inhibiting e con . the rst signal also remains active during this time (see figure 27., page 36 ). note: most low power srams on the market to- day can be used with the m41st87y/w rtc su- pervisor. there are, however some criteria which should be used in making the final choice of an sram to use. the sram must be designed in a way where the chip enable input disables all oth- er inputs to the sram. this allows inputs to the m41st87y/w and srams to be ?don?t care? once v cc falls below v pfd (min). the sram should also guarantee data retention down to v cc =2.0 volts. the chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included. if the sram includes a second chip enable pin (e2), this pin should be tied to v out . if data retention lifetime is a critical parameter for the system, it is important to review the data reten- tion current specifications for the particular srams being evaluated. most srams specify a data retention current at 3.0 volts. manufacturers generally specify a typical condition for room tem- perature along with a worst case condition (gener- ally at elevated temperatures). the system level requirements will determine the choice of which value to use. the data retention current value of the srams can then be added to the i bat value of the m41st87y/w to determine the total current re- quirements for data retention. the available bat- tery capacity for the battery of your choice can then be divided by this current to determine the amount of data retention available. for a further more detailed review of lifetime calcu- lations, please see application note an1012. tamper detection circuit the m41st87y/w provides two independent in- put pins, the tamper pin 1 input (tp1 in ) and tamper pin 2 input (tp2 in ), which can be used to monitor two separate signals which can result in the associated setting of the tamper bits (tb1 and/or tb2, in flag register 0fh) if the tamper enable bits (teb1 and/or teb2) are enabled, for the respective tamper 1 or tamper 2. the tp1 in pin or tp2 in pin may be set to indicate a tamper event has occurred by either 1) closing a switch to ground or v out (normally open), or by 2) opening a switch that was previously closed to ground or v out (normally closed), depending on the state of the tcm x bits and the tpm x bits in the tamper register (14h and/or 15h). tamper register bits (tamper 1 and tamper 2) tamper enable bits (teb1 and teb2). when set to a logic '1,' this bit will enable the tamper de- tection circuit. this bit must be set to '0' in order to clear the associated tamper bits (tb x , in 0fh). note: teb x should be reset whenever the tamper detect condition is modified. tamper bits (tb1 and tb2). if the teb x bit is set, and a tamper condition occurs, the tb x bit will be set to '1.' this bit is ?read-only? and is reset only by setting the teb x bit to '0.' these bits are located in the flags register 0fh. tamper interrupt enable bits (tie1 and tie2). if this bit is set to a logic '1,' the irq /out pin will be activated when a tamper event occurs. this function is also valid in battery back-up if the abe bit (alarm in battery back-up) is also set to '1' (see figure 15., page 16 ). note: in order to avoid an inadvertent activation of the irq /out pin due to a prior tamper event, the flag register (0fh) should be read prior to reset- ting the teb x bit. tamper connect mode bit (tcm1 and tcm2). this bit indicates whether the position of the exter- nal switch selected by the user is in the normally open (tcm x = '1') or normally closed (tcm x = '0') position (see figure 14., page 15 and figure 16., page 16 ). tamper polarity mode bits (tpm1 and tpm2). the state of this bit indicates whether the tamper pin input will be taken high (to v out if tpm x = '1') or low (to v ss if tpm x = '0') during a tamper event (see figure 14., page 15 and figure 16., page 16 ).
15/40 m41st87y, M41ST87W figure 14. tamper detect connection options note: these options are connected to those in table 3 . note: 1. if the clrx ext bit is set, a second tamper to v out (tpm2 = '1') during t clr will not be detected. 2. if the clrx ext bit is set, a second tamper to v out (tpm2 = '1') will trigger automatically. 3. optional external resistor to v cc allows the user to bypass sampling when power is ?on.? table 3. tamper detection truth table note: 1. no battery current drawn during battery back-up. option mode tcm x tpm x i normally open/tamper to gnd (1) 10 ii normally open/tamper to v out (1) 11 iii normally closed/tamper to gnd 0 0 iv normally closed/tamper to v out 01 ai07075 tp in tamper hi (tpm x = 1) tamper lo (tpm x = 0) v out (1) tp in normally closed (tcm x = 0) normally open (tcm x = 1) i. iv. ii. iii. tp in v out (2) tchi/tclo = 0 1m ? 10m ? tchi/tclo = 1 tchi/tclo = 0 tchi/tclo = 1 1m ? 10m ? v out (int) v cc (3)
m41st87y, M41ST87W 16/40 figure 15. tamper detect output options figure 16. basic tamper detect options tamper detect sampling (tds1 and tds2). this bit selects between a 1hz sampling rate or constant monitoring of the tamper input pin(s) to detect a tamper event when the normally closed switch mode is selected. this allows the user to re- duce the current drain when the teb x bit is en- abled while the device is in battery backup (see table 4., page 17 and figure 17., page 18 ). sam- pling is disabled if the tcm x bit is set to logic '1' (normally open). in this case the state of the tds x bit is a ?don?t care.? note: the crystal oscillator must be ?on? for sam- pling to be enabled. ai07821 irq - interrupt the processor on tamper user configuration tp clr - clear external ram on tamper reset out clr - clear 128 bytes internal ram on tamper time stamp tamper event (to rtc) clr1 ext tie 1 clr1 clr2 ext tie 2 clr2 (other reset sources) teb2 tp2 teb1 tp1 ai07818 tamper lo, normally open tamper hi, normally closed user configuration tcm x , tpm x irq - interrupt the processor on tamper tp clr - clear external ram on tamper clr - clear internal ram on tamper time stamp tamper event clrx ext tie x clrx tamper hi, normally open tamper lo, normally closed triggering event tamper event output tcm x , tpm x = 1,1 tcm x , tpm x = 0,0 tcm x , tpm x = 1,0 tcm x , tpm x = 0,1 v cc (v out ) v cc (v out ) v cc (v out )
17/40 m41st87y, M41ST87W tamper current hi/tamper current lo (tchi/ tclo 1 and tchi/tclo 2). this bit selects the strength of the internal pull-up or pull-down used during the sampling of the normally closed condi- tion. the state of the tchi/tclo x bit is a ?don?t care? for normally open (tcm x = '1') mode (see figure 18., page 18 ). ram clear (clr1 and clr2). when either of these bits and the teb x bit are set to a logic '1,' the internal 128 bytes of user ram (see figure 15., page 16 ) will be cleared to all zeros in the event of a tamper condition. the 128 bytes of user ram will be deselected (invalid data will be read) until the corresponding teb x bit is reset to '0.' ram clear external (clr1 ext and clr2 ext ). when either of these bits are set to a logic '1' and the teb x bit is also set to logic '1,' the external sram will be cleared and the rst output enabled (see figure 15., page 16 and figure 20., page 20 ). note: the reset output resulting from a tamper event will be the same as a reset resulting from a power-down condition, a watchdog time-out, or a manual reset (rstin1 or rstin2 ). this is accomplished by forcing tp clr high, which if used to control the inhibit pin of the dc regulator (see figure 20., page 20 ) will also switch off v out , depriving the external sram of power to the v cc pin. v out will automatically be disconnected from the battery if the tamper occurs during battery back-up (see figure 19., page 19 ). by inhibiting the dc regulator, the user will also prevent other inputs from sourcing current to the external sram, allowing it to retain data. the user may optionally connect an inverting charge pump to the v cc pin of the external sram (see figure 20., page 20 ). depending on the pro- cess technology used for the manufacturing of the external sram, clearing the memory may require varying durations of negative potential on the v cc pin. this device configuration will allow the user to program the time needed for their particular appli- cation. control bits clrpw0 and clrpw1 deter- mine the duration tp clr will be enabled (see figure 19., page 19 and table 5., page 19 ). note: when using the inverting charge pump, the user must also provide isolation in the form of two additional small-signal power mosfets. these will isolate the v out pin from both the negative voltage generated by the charge pump during a tamper condition, and from being pulled to ground by the output of the charge pump when it is in shut- down mode (shdn = logic low). the gates of both mosfets should be connected to tp clr as shown in figure 20., page 20 . one n-channel en- hancement mosfet should be placed between the output of the inverting charge pump and the v out of the m41st87. the other mosfet should be an enhancement mode p-channel, and placed between v out of the m41st87 and v cc of the ex- ternal sram. when tp clr goes high after a tamper condition occurs, the n-channel mosfet will turn on and t he p-channel will turn off. during normal operating conditions, tp clr will be low and the p-channel will be on, while the n-channel will be off. table 4. tamper detection current (normally closed - tcm x = '0') note: 1. when calculating battery lifetime, this current should be added to i bat current listed in table 16., page 35 . 2. per tamper detect input tds x tchi/tclo x tamper circuit mode current at 3.0v (typ) (1,2) unit 0 0 continuous monitoring / 10m ? pull-up/-down 0.3 a 0 1 continuous monitoring / 1m ? pull-up/-down 3.0 a 1 0 sampling (1hz) / 10m ? pull-up/-down 0.3 na 1 1 sampling (1hz) / 1m ? pull-up/-down 3.0 na
m41st87y, M41ST87W 18/40 figure 17. tamper detect sampling options figure 18. tamper current options ai07819 tamper lo, normally open tamper hi, normally closed user configuration tds x = 0 tds x = 1 tds x = 0 tds x = 1 tamper hi, normally open tamper lo, normally closed continuous monitoring continuous monitoring continuous monitoring sampled monitoring continuous monitoring sampled monitoring v cc (v out ) v cc (v out ) v cc (v out ) tcm x , tpm x ai07820 tamper lo, normally open tamper hi, normally closed user configuration user configuration user configuration tds x = 0 tds x = 1 tds x = 0 tds x = 1 tamper hi, normally open tamper lo, normally closed continuous monitoring continuous monitoring continuous monitoring sampled monitoring continuous monitoring sampled monitoring v cc (v out ) tp x (tp1, tp2) v cc (v out ) v cc (v out ) tcm x , tpm x tchi/tclo = 0 tchi/tclo = 1 1m ? 10m ? tchi/tclo = 0 tchi/tclo = 1 1m ? 10m ?
19/40 m41st87y, M41ST87W figure 19. tamper output timing (with clr1 ext or clr2 ext = '1') note: 1. if connected to a negative charge pump device, this pin must be isolated from the charge pump by using both n-channel an d p- channel mosfets as illustrated in figure 20., page 20 . 2. if the device is in battery back-up; not on v cc (see ram clear external (clr1 ext and clr2 ext ), page 17 ). 3. if tie x = '1.' 4. if abe = '1.' table 5. tamper detect timing note: 1. with input capacitance = 70pf and resistance = 50 ? . 2. if the of bit is set, t clrd (min) = 0.5ms. symbol parameter clrpw1 clrpw0 min typ max unit t clrd (1) tamper ram clear ext delay x x 1.0 (2) 1.5 2.0 ms t clr tamper clear timing 00 1 s 01 4 s 10 8 s 11 16 s tp clr v out (1) rst tamper event (tb bit set) high-z (2) trec tclr tclrd ai07083 e con irq/out (3) high-z (4)
m41st87y, M41ST87W 20/40 figure 20. ram clear hardware hookup note: 1. most inverting charge pumps drive out to ground when device shut down is enabled (shdn = logic low). therefore, an n-channel enhancement mode mosfet should be used to isolate the out pin from the v out of the m41st87. 2. in order to avoid turning on an on-chip parasitic diode when driving v out negative, a p-channel enhancement mode mosfet should be used to isolate the v out pin from the negative voltage generated by the inverting charge pump. ai07804 v cc pfo 1 ex scl m41st87y/w wdi rstin1 rstin2 pfi 1 pfi 2 v ss v bat f 32k irq/out sqw/ft rst v out e con sda cap+ cap? inverting charge pump shdn out in tp1 in tp clr tp2 in pushbutton reset pfo 2 low-power sram v cc negative output (?1 x v in ) e to rst to led display (2) (1) to nmi to int to 32khz inhibit 5v regulator v cc v in
21/40 m41st87y, M41ST87W tamper detection operation the tamper pins are triggered based on the state of an external switch. two switch mode options are available, ?normally open? or ?normally closed,? based on the setting of the tamper con- nect mode bit (tcm x ). if the selected switch mode is normally open (tcm x = '1'), the tamper pin will be triggered by being connected to v ss (if the tpm x bit is set to '0') or to v cc (if the tpm x bit is set to '1'), through the closing of the external switch. when the external switch is closed, the tamper bit will be immediately set, allowing the user to determine if the device has been physically tampered with. if the selected switch mode is nor- mally closed (tcm x = '0'), the tamper pin will be triggered by being pulled to v ss or to v out (de- pending on the state of the tpm x bit), through an internal pull-up/pull-down resistor as a result of opening the external switch. when a tamper event occurs, the tamper bits (tb1 and/or tb2) will be immediately set if teb x = '1.' if the tamper interrupt enable bit (tie x ) is set to a '1,' the irq /out pin will also be activated. the irq /out output is cleared by a read of the flags register (as seen in figure 23., page 26 ), a reset of the tie bit to '0,' or the rst output is enabled. note: in order to avoid an inadvertent activation of the irq /out pin due to a prior tamper event, the flag register (0fh) should be read prior to reset- ting the teb x bit. the tamper bits are ?read only? bits and are reset only by writing the tamper enable bit (teb x ) to '0.' the tamper detect function operates both under normal power, and in battery back-up. even if the trigger event occurs during a power-down condi- tion, the bit will be set correctly. sampling as the switch mode normally closed (tcm x ='0') requires a greater amount of current to maintain constant monitoring, the m41st87y/w offers a programmable tamper detect sampling bit (tds x ) to reduce the current drawn on v cc or v bat (see figure 17., page 18 ). when enabled, the sampling frequency is once per second (1hz), for approximately 1ms. when teb x is disabled, no current will be drawn by the tamper detection circuit. after a tamper event has been detected, no additional current will be drawn. note: the oscillator must be running for tamper detection to operate in the sampling mode. if the oscillator is stopped, the tamper detection circuit will revert to constant monitoring. note: sampling in the tamper high mode (tpm x = '1') may be bypassed while on v cc by connecting the tpx in pin to v cc through an exter- nal resistor. this will allow constant monitoring when v cc is ?on? and revert to sampling when in battery back-up (see figure 14., page 15 ). internal tamper pull-up/down current depending on the capacitive and resistive loading of the tamper pin input (tp xin ), the user may re- quire more or less current from the internal pull-up/ down used when monitoring the normally closed switch mode. the state of the tamper current hi/ tamper current low bit (tchi/tclo x ) deter- mines the sizing of the internal pull-up/-down. tchi/tclo x = '1' uses a 1m ? pull-up/-down re- sistor, while tchi/tclo x = '0' uses a 10m ? pull- up/-down resistor (see figure 18., page 18 ). note: no additional, external capacitance is re- quired on the tamper input pin. tamper event time-stamp regardless of which tamper occurs first, not only will the appropriate tamper bit be set, but the event will also be automatically time-stamped. this is accomplished by freezing the normal up- date of the clock registers (00h through 07h) im- mediately following a tamper event. thus, when tampering occurs, the user may first read the time registers to determine exactly when the tamper event occurred, then re-enable the clock update to the current time (and reset the tamper bit, tb x ) by resetting the tamper enable bit (teb x ). the time update will then resume and the clock can be read to determine the current time. both tamper enable bits (teb x ) must always be set to '0' in order to read the current time. in the event of multiple tampers, the time-stamp will reflect the initial tamper event. note: if the teb x bit is set, the tamper event time-stamp will take precedence over the power down time-stamp (see power-down time- stamp, page 22 ) and the ht bit (halt update) will not be set during the power-down event. if both are needed, the power down time-stamp may be accomplished by writing the time into the general purpose ram memory space when pfo is assert- ed.
m41st87y, M41ST87W 22/40 clock operation the eight byte clock register (see table 6., page 23 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of sec- onds, seconds, minutes, and hours are contained within the first four registers. note: a write to any clock register will result in the tenths/hundredths of seconds being reset to ?00,? and tenths/hundredths of seconds cannot be written to any value other than ?00.? bits d6 and d7 of clock register 03h (century/ hours register) contain the century bit 0 (cb0) and century bit 1 (cb1). bits d0 through d2 of register 04h contain the day (day of week). reg- isters 05h, 06h, and 07h contain the date (day of month), month, and years. the ninth clock register is the control register (this is described in the clock calibration section). bit d7 of register 01h contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is ex- pected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. when reset to a '0' the oscillator re- starts within one second (typical). note: a write to any location within the first eight bytes of the clock register (00h-07h), includ- ing the ofie bit, clrpw0 bit, clrpw1 bit, ths bit, and so forth, will result in an update of the sys- tem clock and a reset of the divider chain. this could result in a significant corruption of the cur- rent time, especially if the ht bit (see ?power down time-stamp? section) has not been previ- ously reset. these non-clock related bits should be written prior to setting the clock, and remain un- changed until such time as a new clock time is also written. the eight clock registers may be read one byte at a time, or in a sequential block. the control reg- ister (address location 08h) may be accessed in- dependently. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock ad- dress is being read, an update of the clock regis- ters will be halted. this will prevent a transition of data during the read. power-down time-stamp upon power-up following a power failure, the halt update bit (ht) will automatically be set to a '1.' this will prevent the clock from updating the time- keeper ? registers, and will allow the user to read the time of the power-down event. note: when the ht bit is set or a tamper event oc- curs, the tenths/hundredths of a second register (00h) will automatically be reset to a value of ?00.? all other date and time registers (01h - 07h) will re- tain the value last updated prior to the power-down or tamper event. the internal clock remains accu- rate and no time is lost as a result of the zeroing of the tenth/hundredths of a second register. when updates are resumed (due to resetting the ht bit or teb bit), the correct time will be dis- played. resetting the ht bit to a '0' will allow the clock to update the tim ekeeper registers with the cur- rent time. note: if the teb bit is set, the power down time- stamp will be disabled, and the tamper event time-stamp will take precedence (see tamper detection operation, page 21 ). timekeeper ? registers the m41st87y/w offers 22 internal registers which contain clock, control, alarm, watchdog, flag, square wave, and tamper data. the clock registers are memory locations which contain ex- ternal (user accessible) and internal copies of the data (usually referred to as biport ? timekeep- er cells). the external copies are independent of internal functions except that they are updated pe- riodically by the simultaneous transfer of the incre- mented internal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address (00h to 07h). the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei- ther due to a stop condition or when the pointer increments to a non-clock or ram address. timekeeper and alarm registers store data in bcd format. control, watchdog and square wave registers store data in binary format.
23/40 m41st87y, M41ST87W table 6. timekeeper ? register map keys: 0 = must be set to zero 32ke = 32khz output enable bit abe = alarm in battery back-up mode enable bit af = alarm flag (read only) afe = alarm flag enable bit bl = battery low flag (read only) bmb0-bmb4 = watchdog multiplier bits cb0-cb1 = century bits clr (1 and 2) = ram clear bits clr (1 and 2) ext = ram clear external bits clrpw0 = ram clear pulse width 0 bit clrpw1 = ram clear pulse width 1 bit ft = frequency test bit ht = halt update bit of = oscillator fail bit ofie = oscillator fail interrupt enable bit out = output level pfod = power-fail output open drain bit rb0-rb1 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits rs0-rs3 = sqw frequency s = sign bit sqwe = square wave enable sqwod = square wave open drain bit st = stop bit tb (1 and 2) = tamper bits (read only) tchi/tclo (1 and 2) = tamper current hi/tamper current low bits tcm (1 and 2) = tamper connect mode bits tds (1 and 2) = tamper detect sampling bits teb (1 and 2) = tamper enable bits ths = threshold bit tie (1 and 2) = tamper interrupt enable bits tpm (1 and 2) = tamper polarity mode bits tr = t rec bit wds = watchdog steering bit wdf = watchdog flag (read only) addr data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10s/100s seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h ofie 10 minutes minutes minutes 00-59 03h cb1 cb0 10 hours hours (24 hour format) century/ hours 0-1/ 00-23 04h tr ths clrpw1 clrpw0 32ke day of week day 01-7 05h pfod 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out ft s calibration control 09h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe abe al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 ht ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 bl 0 of tb1 tb2 flags 10h 0 0 0 0 0 0 0 0 reserved 11h 0 0 0 0 0 0 0 0 reserved 12h 0 0 0 0 0 0 0 0 reserved 13hrs3rs2rs1 rs0sqwod0 0 0 sqw 14h teb1 tie1 tcm1 tpm1 tds1 tchi/ tclo 1 clr1 ext clr1 tamper1 15h teb2 tie2 tcm2 tpm2 tds2 tchi/ tclo 2 clr2 ext clr2 tamper2 16h-1dh rom serial number 8-byte 1eh-1fh reserved 2-byte 20h-9fh 128 user bytes
m41st87y, M41ST87W 24/40 calibrating the clock the m41st87y/w is driven by a quartz controlled oscillator with a nominal frequency of 32,768hz. the devices are tested not exceed 35 ppm (parts per million) oscillato r frequency error at 25 o c, which equates to about 1.53 minutes per month. when the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25c. the oscillation rate of crystals changes with tem- perature (see figure 21., page 25 ). therefore, the m41st87y/w design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in figure 22., page 25 . the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register (08h). these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indi- cates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 osc illator cycles. if a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given m41st87y/w may re- quire. the first involves setting the clock, letting it run for a month and comparing it to a known accurate ref- erence and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934, ?tim ekeep- er ? calibration.? this allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final prod- uct is packaged in a non-user serviceable enclo- sure. the designer could provide a simple utility that accesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the sqw/ft pin. the pin will toggle at 512hz, when the stop bit (st) is '0,' the frequency test bit (ft) is '1,' and sqwe is '0.' any deviation from 512hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124hz would indicate a +20 ppm oscillator frequency error, requiring a ?10 (xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequen- cy. if the sqwod bit = '1,' the sqw/ft pin is an open drain output which requires a pull-up resistor to v cc for proper operation. a 500 to10k resistor is recommended in order to control the rise time. the ft bit is cleared on power-down.
25/40 m41st87y, M41ST87W figure 21. crystal accuracy across temperature figure 22. calibration waveform ai07888 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 = ?0.036 ppm/ c 2 0.006 ppm/ c 2 k ? f = k x (t ? t o ) 2 f t o = 25 c 5 c ai00594b normal positive calibration negative calibration
m41st87y, M41ST87W 26/40 setting alarm clock registers address locations 0ah-0eh contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. it can also be pro- grammed to go off while the m41st87y/w is in the battery back-up to serve as a system wake-up call. bits rpt5?rpt1 put the alarm in the repeat mode of operation. table 7., page 26 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5?rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set, the alarm condi- tion activates the irq /out pin as shown in figure 24., page 27 . to disable alarm, write '0' to the alarm date register and to rpt5?rpt1. note: if the address pointer is allowed to incre- ment to the flag register address, an alarm con- dition will not cause the interrupt/flag to occur until the address pointer is moved to a different ad- dress. it should also be noted that if the last ad- dress written is the ?alarm seconds,? the address pointer will increment to the flag address, causing this situation to occur. the irq /out output is cleared by a read to the flags register. a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' the irq /out pin can also be activated in the bat- tery back-up mode. the irq /out will go low if an alarm occurs and both abe (alarm in battery back-up mode enable) and afe are set. the abe and afe bits are reset during power-up, therefore an alarm generated during power-up will only set af. the user can read th e flag register at system boot-up to determine if an alarm was generated while the m41st87y/w was in the deselect mode during power-up. figure 24., page 27 illustrates the back-up mode alarm timing. figure 23. alarm interrupt reset waveform table 7. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 11111once per second 11110once per minute 11100once per hour 11000once per day 10000once per month 00000once per year ai07086 irq/out active flag 0fh 0eh 10h high-z
27/40 m41st87y, M41ST87W figure 24. back-up mode alarm waveform watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolu- tion, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. the amount of time- out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (for example: writing 00001110 in the watchdog reg- ister = 3*1 or 3 seconds). note: the accuracy of the timer is within the se- lected resolution. if the processor does not reset the timer within the specified period, the m41st87y/w sets the wdf (watchdog flag) and generates a watchdog inter- rupt or a microprocessor reset. the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a '0,' the watchdog will activate the irq /out pin when timed-out. when wds is set to a '1,' the watchdog will output a negative pulse on the rst pin for t rec . the watchdog register, ft, afe, abe and sqwe bits will reset to a '0' at the end of a watchdog time-out when the wds bit is set to a '1.' the watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (wdi) or 2) the microprocessor can perform a write of the watchdog register. the time-out period then starts over. note: the wdi pin should be tied to v ss if not used. in order to perform a software reset of the watch- dog timer, the original time-out period can be writ- ten into the watchdog register, effectively restarting the count-down cycle. should the watchdog timer time-out, and the wds bit is programmed to output an interrupt, either a transition of the wdi pin, or a value of 00h needs to be written to the watchdog register in order to clear the irq /out pin. this will also disable the watchdog function until it is again programmed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. ai07087 v cc irq/out v pfd abe, afe bits in interrupt register af bit in flags register high-z v so high-z trec
m41st87y, M41ST87W 28/40 square wave output the m41st87y/w offers the user a programma- ble square wave function which is output on the sqw/ft pin. rs3-rs0 bits located in 13h estab- lish the square wave output frequency. these fre- quencies are listed in table 8 . once the selection of the sqw frequency has been completed, the sqw/ft pin can be turned on and off under soft- ware control with the square wave enable bit (sqwe) located in register 0ah. the sqw/ft output is programmable as an n- channel, open drain output driver, or a full-cmos output driver. by setting the square wave open drain bit (sqwod) to a '1,' the output will be con- figured as an open drain (with i ol as specified in table 16., page 35 ). when sqwod is set to '0,' the output will be configured as full-cmos (sink and source current as specified in table 16., page 35 ). note: when configured as open drain (sqwod = '1'), the sqw/ft pin requires an external pull-up resistor. table 8. square wave output frequency full-time 32khz square wave output the m41st87y/w offers the user a special 32khz square wave function which defaults to output on the f 32k pin (pin 21) as long as v cc v so , and the oscillator is running (st bit = '0'). this function is available within one second (typ) of initial power- up and can only be disabled by setting the 32ke bit to '0' or the st bit to '1.' if not used, the f 32k pin should be disconnected and allowed to float. note: the f 32k pin is an open drain which requires an external pull-up resistor. square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none? 0 0 0 1 32.768 khz 00108.192khz 00114.096khz 01002.048khz 01011.024khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
29/40 m41st87y, M41ST87W power-on reset the m41st87y/w continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for t rec after v cc passes v pfd (max). the rst pin is an open drain output and an appro- priate pull-up resistor should be chosen to control rise time. note: a power-on reset will re sult in resetting the following control bits to '0': ofie, afe, abe, sqwe, ft, wds, bmb0-bmb4, rb0, rb1, tie1, and tie2 (see table 12., page 32 ). reset inputs (rstin1 & rstin2 ) the m41st87y/w provides two independent in- puts which can generate an output reset. the function of these resets is identical to a reset gen- erated by a power cycle. table 9 and figure 25 il- lustrate the ac reset characteristics of this function. pulses shorter than t r1 and t r2 will not generate a reset condition. rstin1 and rstin2 are each internally pulled up to v cc through a 100k ? resistor. figure 25. rstin1 & rstin2 timing waveforms table 9. reset ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. pulse widths of less than 100ns will result in no reset (for noise immunity). 3. programmable (see table 11., page 31 ). same function as power-on reset. symbol parameter (1) min max unit t r1 (2) rstin1 low to rst low (min pulse width) 100 200 ns t r2 (2) rstin2 low to rstin2 high (min pulse width) 100 200 ns t rec (3) rstin1 or rstin2 high to rst high 96 98 (3) ms ai07072 rstin1 rst rstin2 tr1 trec hi-z tr2 trec hi-z
m41st87y, M41ST87W 30/40 power-fail comparators (1 and 2) two power-fail inputs (pfi 1 and pfi 2 ) are com- pared to an internal reference voltage (1.25v). if either pfi 1 or pfi 2 is less than the power-fail threshold (v pfi ), the associated power-fail output (pfo 1 or pfo 2 ) will go low. this function is intend- ed for use as an under-voltage detector to signal a failing power supply. typically pfi 1 and pfi 2 are connected through external voltage dividers (see figure 5., page 8 ) to either the unregulated dc in- put (if it is available) or the regulated output of the v cc regulator. the voltage divider can be set up such that the voltage at pfi 1 or pfi 2 falls below v pfi several milliseconds before the regulated v cc input to the m41st87y/w or the microproces- sor drops below the minimum operating voltage. during battery back-up, the power-fail comparator turns off and pfo 1 and pfo 2 go (or remain) low. this occurs after v cc drops below v pfd (min). when power returns, pfo 1 and pfo 2 are forced high, irrespective of v pfi for the write protect time (t rec ), which is the time from v pfd (max) until the in- puts are recognized. at the end of this time, the power-fail comparator is enabled and pfo 1 and pfo 2 follow pfi 1 and pfi 2 . if the comparator is unused, pfi 1 or pfi 2 should be connected to v ss and the associated pfo 1 or pfo 2 left unconnect- ed. power-fail outputs the pfo 1 and pfo 2 outputs are programmable as n-channel, open drain output drivers, or full- cmos output drivers. by setting the power-fail output open drain bit (pfod) to a '1,' the output will be configured as open drain (with i ol as spec- ified in table 16., page 35 ). when pfod is set to '0,' the outputs will be configured as full-cmos (sink and source current as specified in table 16., page 35 ). note: when configured as open drain (pfod = '1'), pfo 1 and pfo 2 will require an external pull- up resistor. century bits these two bits will increment in a binary fashion at the turn of the century, and handle leap years cor- rectly. see table 10., page 31 for additional expla- nation. output driver pin when the tie bit, ofie bit, afe bit, and watch- dog register are not set to generate an interrupt, the irq /out pin becomes an output driver that re- flects the contents of d7 of the control register. in other words, when d7 (out bit) is a '0,' then the irq /out pin will be driven low. with the abe bit set to '1,' the out pin will continue to be driven low in battery back-up. note: the irq /out pin is an open drain which re- quires an external pull-up resistor. battery low warning the m41st87y/w automatically performs battery voltage monitoring upon power-up and at factory- programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 0fh, will be asserted if the battery voltage is found to be less than approximately 2.5v. the bl bit will remain asserted until completion of bat- tery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up se- quence, this indicates that the battery is below ap- proximately 2.5 volts and may not be able to maintain data integrity in the sram. data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. however, data is not com- promised due to the fact that a nominal v cc is supplied. in order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. the battery may be re- placed while v cc is applied to the device. the m41st87y/w only monitors the battery when a nominal v cc is applied to the device. thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. t rec bit bit d7 of clock register 04h contains the t rec bit (tr). t rec refers to the automatic continuation of the deselect time after v cc reaches v pfd . this al- lows for a voltage settling time before writes may again be performed to the device after a pow- er-down condition. the t rec bit will allow the user to set the length of this deselect time as defined by table 11., page 31 . electronic serial number the m41st87y/w has a unique 8-byte lasered, serial number with parity. this serial number is ?read only? and is generated such that no two de- vices will contain an identical number.
31/40 m41st87y, M41ST87W oscillator stop detection if the oscillator fail (of) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date da- ta. this bit will be set to '1' any time the oscillator stops. the following conditions can cause the of bit to be set: ? the first time power is applied (defaults to a '1' on power-up). ? the voltage present on v cc or battery is insuffi- cient to support oscillation. ? the st bit is set to '1.' if the oscillator fail interrupt enable bit (ofie) is set to a '1,' the irq /out pin will also be activated. the irq /out output is cleared by resetting the of bit to '0,' resetting the ofie bit to '0,' or the rst output is enabled (not by reading the flag register). the of bit will remain set to '1' until written to logic '0.' the oscillator must start and have run for at least 4 seconds before attempting to reset the of bit to '0.' this function operates both under normal power and in battery back-up. if the trigger event occurs during a power-down condition, this bit will be set correctly. note: the abe bit must be set to '1' for the irq / out pin to be activated in battery back-up. initial power-on defaults see table 12., page 32 . table 10. century bits examples note: 1. leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. the on ly exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not). table 11. t rec definitions note: 1. default setting cb0 cb1 leap year? example (1) 00yes2000 0 1 no 2100 1 0 no 2200 1 1 no 2300 t rec bit (tr) stop bit (st) t rec time units min max 0096 98 (1) ms 0 1 40 200 ms 1 x 50 2000 s
m41st87y, M41ST87W 32/40 table 12. default values note: all other control bits are undetermined. note: 1. uc = unchanged. 2. ? = v cc rising; ? = v cc falling. 3. when teb x is set to '1,' the ht bit will not be set on power-down (tamper time-stamp will have precedence). 4. wds, bmb0-bmb4, rb0, rb1. 5. 32khz output valid only on v cc . condition tr st of ofie ht (3) out ft afe initial power-up 00101100 subsequent power-up (with battery back-up) (1,2) uc uc uc 0 ? 1 ? uc 0 ? 0 ? condition abe sqwe sqwod pfod watchdog register (4) initial power-up 0011 0 subsequent power-up (with battery back-up) (1,2) 0 ? 0 ? uc uc 0 ? condition 32ke ths teb1 and 2 tcm1 and 2 tpm1 and 2 tds1 and 2 initial power-up 1 (5) 00000 subsequent power-up (with battery back-up) (1) uc uc uc uc uc uc condition tchi/tclo 1 and 2 clr1 and 2 tie1 and 2 clrpw0 clrpw1 clr1 ext and clr2 ext initial power-up 000000 subsequent power-up (with battery back-up) (1) uc uc 0 ? uc uc uc
33/40 m41st87y, M41ST87W maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 13. absolute maximum ratings note: 1. reflow at peak temperature of 240c (total thermal budget not to exceed 180c between 90 to 150 seconds). caution: negative undershoots below ?0.3v are not allowed on any pin while in the battery back-up mode. symbol parameter value unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c t sld (1) lead solder temperature for 10 seconds 240 c v io input or output voltage ?0.3 to v cc +0.3 v v cc supply voltage m41st87y ?0.3 to 7.0 v M41ST87W ?0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
m41st87y, M41ST87W 34/40 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 14. dc and ac measurement conditions note: output high z is defined as the point where data is no longer driven. figure 26. ac testing input/output waveforms note: 50pf for M41ST87W. table 15. capacitance note: 1. effective capacitance measured with power supply at 5v. sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs are deselected. parameter m41st87y M41ST87W v cc supply voltage 4.5 to 5.5v 2.7 to 3.6v ambient operating temperature ?40 to 85c ?40 to 85c load capacitance (c l ) 100pf 50pf input rise and fall times 50ns 50ns input pulse voltages 0.2 to 0.8v cc 0.2 to 0.8v cc input and output timing ref. voltages 0.3 to 0.7v cc 0.3 to 0.7v cc ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc symbol parameter (1,2) min max unit c in input capacitance 7 pf c out (3) output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns
35/40 m41st87y, M41ST87W table 16. dc characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. measured with v out and e con open. not including tamper detection current (see table 4., page 17 ). 3. rstin1 and rstin2 internally pulled-up to v cc through 100k ? resistor. wdi internally pulled-down to v ss through 100k ? resistor. 4. outputs deselected. 5. external sram must match rtc supervisor chip v cc specification. 6. for rechargeable back-up, v bat (max) may be considered v cc . 7. for pfo 1 and pfo 2 (if pfod = '0'), sqw/ft (if sqwod = '0'), and tp clr pins (cmos). 8. conditioned output (e con ) can only sustain cmos leakage current in the battery back-up mode. higher leakage currents will re- duce battery life. 9. tp clr output can source ?300a (typ) for v bat = 2.9v. 10. for irq /out, sqw/ft (if sqwod = '1'), pfo 1 and pfo 2 (if pfod = '1'), rst , sda, and f 32k pins (open drain). sym parameter test condition (1) m41st87y M41ST87W unit min typ max min typ max i bat (2) battery current osc on t a = 25c, v cc = 0v, v bat = 3v 500 700 500 700 na battery current osc off 50 50 na i cc1 supply current f = 400khz 1.4 0.75 ma i cc2 supply current (standby) scl, sda = v cc ? 0.3v 10.50ma i li (3) input leakage current 0v v in v cc 1 1 a input leakage current (pfi) ?25 2 25 ?25 2 25 na i lo (4) output leakage current 0v v in v cc 1 1 a i out1 (5) v out current (active) v out1 > v cc ? 0.3v 175 100 ma i out2 v out current (battery back-up) v out2 > v bat ? 0.3v 100 100 a v ih input high voltage 0.7v cc v cc + 0.3 0.7v cc v cc + 0.3 v v il input low voltage ?0.3 0.3v cc ?0.3 0.3v cc v v bat battery voltage 2.5 3.0 3.5 (6) 2.5 3.0 3.5 (6) v v oh (7) output high voltage i oh = ?1.0ma 2.4 2.4 v pull-up supply voltage (open drain) irq /out, rst , f 32k 5.5 3.6 v v ohb (8) v oh (battery back- up) i out2 = ?1.0a (9) 2.9 2.9 v v ol output low voltage i ol = 3.0ma 0.4 0.4 v output low voltage (open drain) (10) i ol = 10ma 0.4 0.4 v v pfd power fail deselect ths bit = 0 4.20 4.35 4.50 2.55 2.62 2.70 v ths bit = 1 4.50 4.60 4.75 2.80 2.88 3.00 v v pfi1 pfi input threshold v cc = 5v(y) v cc = 3v(w) 1.225 1.250 1.275 1.225 1.250 1.275 v pfi hysteresis pfi rising 20 70 20 70 mv v pfi2 pfi input threshold v cc = 5v(y) v cc = 3v(w) 1.225 1.250 1.275 1.225 1.250 1.275 v pfi hysteresis pfi rising 20 70 20 70 mv v so battery back-up switchover 2.5 2.5 v r sw switch resistance on tamper pin 500 500 ?
m41st87y, M41ST87W 36/40 figure 27. power down/up mode ac waveforms table 17. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200s after v cc passes v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. 4. programmable (see table 11., page 31 ) symbol parameter (1) min typ max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t pd ex at v ih before power down 0s t pfd pfi to pfo propagation delay 15 25 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t rec power up deselect time 96 98 (4) ms ai07085 v cc inputs (per control input) outputs don't care high-z tf tfb tr tpd trb valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so trec rst e con pfo valid valid
37/40 m41st87y, M41ST87W package mechanical information figure 28. sox28 ? 28-lead plastic small outline, 300mils, embedded crystal outline note: drawing is not to scale. table 18. sox28 ? 28-lead plastic small outline, 300mils, embedded crystal, mechanical data symbol millimeters inches typ min max typ min max a 2.44 2.69 0.096 0.106 a1 0.15 0.31 0.006 0.012 a2 2.29 2.39 0.090 0.094 b 0.41 0.51 0.016 0.020 c 0.20 0.31 0.008 0.012 d 17.91 18.01 0.705 0.709 ddd 0.10 0.004 e 7.57 7.67 0.298 0.302 e1.27? ?0.050? ? h 10.16 10.52 0.400 0.414 l 0.51 0.81 0.020 0.032 0 8 0 8 n 28 28 e 14 e d c h 15 28 1 b so-e a1 l a1 h x 45? a a2 ddd
m41st87y, M41ST87W 38/40 part numbering table 19. ordering information scheme note: 1. the sox28 package includes an embedded 32,768hz crystal. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m41st 87y mx 6 device type m41st supply voltage and write protect voltage 87y = v cc = 4.75 to 5.5v ths bit = '1': 4.50v v pfd 4.75v v cc = 4.5 to 5.5v ths bit = '0': 4.20v v pfd 4.50v 87w = v cc = 3.0 to 3.6v; ths bit = '1': 2.80v v pfd 3.00v v cc = 2.7 to 3.6v; ths bit = '0': 2.55v v pfd 2.70v package mx (1) = sox28 temperature range 6 = ?40 to 85c shipping method blank = tubes tr = tape & reel
39/40 m41st87y, M41ST87W revision history table 20. document revision history m41st87, m41st87y, M41ST87W, 41st87, 41st87y, 41st87w, st87, st 87y, st87w, supervisor, superviso r, supervisor, supervisor, supe rvisor, supervisor, supervisor, su- pervisor, supervisor, supervisor, superviso r, supervisor, supervisor, supervisor, su pervisor, supervisor, supervisor, superviso r, supervisor, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, microprocessor, microprocessor, microprocessor, micro- processor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, micr oprocessor, microprocessor, microprocessor, microprocessor, microproces- sor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microproce ssor, microprocessor, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, tamper, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, detect, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, ic, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscilla tor, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscil- lator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, c rystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, crystal, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, al arm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, ala rm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, al arm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, ala rm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, al arm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, ala rm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, al arm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, i rq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, irq, pf i, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfo, pf o, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset , reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, reset, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, ba ttery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, b attery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, b attery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, switchover, switchover, switchover, switchover, switchover, switchover, s witchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, com- parator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator , comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, compara tor, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, soic, soic, soic, soic, soic, s oic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5 v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v, 3v date version revision details may 2002 1.0 first issue 23apr-03 2.0 document promoted to preliminary data 10-jul-03 2.1 update tamper information (figure 4 , 5 , 14 , 15 , 16 ; table 16 , 4 , 11 ) 11-sep-03 2.2 update electrical, charge pump, and clock information (table 16 ; figure 5 , 19 , 20 ) 15-jun-04 3.0 reformatted; added lead-free information; updated characteristics (figure 3 ; table 1 , 13 , 16 , 19 ) 7-sep-04 4.0 update maximum ratings (table 13 )
m41st87y, M41ST87W 40/40 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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